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Abstract #

Large language model inference comprises two computationally distinct phases — prefill and decode — that exhibit fundamentally different hardware utilization profiles. Colocating both phases on the same GPU leads to resource contention and suboptimal utilization, a problem that disaggregated architectures address by separating prefill and decode onto dedicated hardware pools. This article investigates three research questions: whether disaggregation reliably improves time-to-first-token (TTFT) under production workloads, how KV cache transfer overhead constrains architectural choices, and what GPU allocation strategies maximize throughput across heterogeneous workloads. Drawing on published benchmarks from DistServe, Splitwise, Mooncake, and ServerlessPD, we find that disaggregation achieves 1.4-2.3x TTFT speedup but introduces non-trivial KV transfer costs that scale linearly with context length. Optimal prefill-to-decode GPU ratios are workload-dependent, with chatbot workloads peaking at 50% prefill allocation and summarization workloads preferring 40%. These findings have direct implications for the AI Memory series, establishing that memory transfer architecture is the primary bottleneck in disaggregated inference systems.

1. Introduction #

In the previous article, we examined semantic prompt caching and its ability to move beyond exact-match lookups to enable fuzzy reuse of cached KV states (Ivchenko, 2026^[2]). That work revealed that cache hit rates depend critically on the infrastructure that stores and transfers KV cache data. This article shifts focus from cache reuse policy to the architectural question of how prefill and decode computation should be physically organized across hardware.

Modern LLM serving systems face a fundamental tension. The prefill phase processes all input tokens in parallel, making it compute-bound with high arithmetic intensity. The decode phase generates tokens autoregressively one at a time, making it memory-bandwidth-bound with low compute utilization (Patel et al., 2024^[3]). When both phases share the same GPU, decode batches are disrupted by prefill operations, inflating tail latency, and prefill throughput is constrained by decode memory reservations (Patel et al., 2025).

Disaggregated architectures resolve this by assigning prefill and decode to separate GPU pools connected via high-speed interconnects. After prefill completes, the generated KV cache is transferred to a decode instance that continues generation. This separation enables independent scaling and hardware specialization — but introduces KV cache transfer as a new bottleneck (Qin et al., 2025^[4]).

Research Questions #

RQ1: Does prefill-decode disaggregation reliably improve TTFT compared to colocated serving under realistic production workloads?

RQ2: How does KV cache transfer overhead scale with context length and interconnect technology, and when does it negate disaggregation benefits?

RQ3: What is the optimal GPU allocation ratio between prefill and decode pools for different workload distributions?

These questions matter for the AI Memory series because disaggregation determines how KV cache — the central data structure of LLM memory — flows between computation stages.

2. Existing Approaches (2026 State of the Art) #

2.1 Inter-GPU Disaggregation #

The foundational approach assigns prefill and decode to separate GPU instances connected via network. DistServe, presented at OSDI 2024, demonstrated that disaggregating prefill and decode improves goodput by up to 2x by eliminating phase interference (Patel et al., 2024^[3]). The key insight was that prefill and decode have orthogonal scaling requirements: prefill benefits from tensor parallelism across GPUs, while decode benefits from larger batch sizes on fewer GPUs.

Splitwise extended this to heterogeneous hardware, showing that prefill instances can use compute-optimized GPUs while decode instances use memory-bandwidth-optimized GPUs (Patel et al., 2025). The approach achieved 1.4x improvement in per-dollar throughput by matching hardware to phase requirements.

2.2 KV-Cache-Centric Disaggregation #

Mooncake, developed by Moonshot AI, introduced a KV-cache-centric disaggregated architecture where the KV cache pool is a first-class distributed resource. Rather than transferring KV caches after prefill, Mooncake manages cache placement proactively using a conductor that optimizes for locality and reuse (Qin et al., 2025^[4]). This approach reduced KV transfer overhead by 35-50% compared to naive transfer schemes.

2.3 Serverless Disaggregation #

ServerlessPD introduced RDMA-codesigned disaggregation for serverless LLM inference, where prefill and decode run as independent functions with zero-copy KV transfer via RDMA (Wu et al., 2025^[5]). This achieved the highest reported TTFT improvement of 2.3x but requires specialized RDMA-capable networking infrastructure.

2.4 Intra-GPU Disaggregation #

Recent work explores disaggregation within a single GPU, using spatial or temporal multiplexing to run prefill and decode concurrently. DynamicAttention proposed adaptive KV cache management for intra-GPU disaggregation, dynamically partitioning GPU resources between phases based on workload (Li et al., 2025^[6]). ELLIE demonstrated that even edge devices benefit from prefill-decode splitting, achieving energy savings of 20-30% on mobile inference chips (Kim et al., 2025^[7]).

2.5 Hardware-Specialized Approaches #

CXL-SpecKV introduced a disaggregated FPGA-based KV cache using Compute Express Link (CXL) memory pooling for datacenter LLM serving (Chen et al., 2026^[8]). SPAD proposed specialized hardware accelerators for prefill and decode stages, showing that purpose-built silicon achieves 1.6x improvement over GPU-based disaggregation.

flowchart TD
    A[Disaggregated Serving Approaches] --> B[Inter-GPU]
    A --> C[Intra-GPU]
    A --> D[Hardware-Specialized]
    B --> B1[DistServe: Goodput-optimized]
    B --> B2[Splitwise: Heterogeneous HW]
    B --> B3[Mooncake: KV-cache-centric]
    B --> B4[ServerlessPD: RDMA serverless]
    C --> C1[DynamicAttention: Adaptive partitioning]
    C --> C2[DuetServe: Harmonized scheduling]
    D --> D1[CXL-SpecKV: FPGA + CXL memory]
    D --> D2[SPAD: Custom accelerators]

3. Quality Metrics and Evaluation Framework #

3.1 Metrics Definition #

To evaluate disaggregated architectures, we adopt metrics from the serving systems literature:

Time-to-First-Token (TTFT): The latency from request arrival to the first generated token. This directly measures prefill efficiency and is the primary beneficiary of disaggregation (Wu et al., 2025^[5]).

Time-Per-Output-Token (TPOT): The average inter-token latency during decode. Disaggregation should maintain or improve TPOT by eliminating prefill interference with decode batches.

KV Transfer Overhead: The time required to move KV cache state from prefill to decode instances. This is the cost of disaggregation, measured in milliseconds as a function of context length and interconnect bandwidth (Qin et al., 2025^[4]).

GPU Utilization: The fraction of GPU compute capacity actively performing useful work. Disaggregation targets improved utilization by matching phase-specific workloads to hardware capabilities.

Normalized Throughput: End-to-end requests per second relative to the colocated baseline, capturing the net effect of all factors.

RQ	Metric	Source	Threshold
RQ1	TTFT Speedup	DistServe, Splitwise benchmarks	>1.3x over colocated
RQ2	KV Transfer Time (ms)	Mooncake, ServerlessPD measurements	<10% of total latency
RQ3	Normalized Throughput	Multi-system comparison	>0.9 at optimal ratio

graph LR
    RQ1 --> M1[TTFT Speedup] --> E1[Compare across 6 systems]
    RQ2 --> M2[KV Transfer ms] --> E2[Model by interconnect type]
    RQ3 --> M3[Throughput vs GPU ratio] --> E3[Per-workload optimization]

3.2 Evaluation Methodology #

We synthesize results from published papers rather than running independent benchmarks. Where papers report different metrics or experimental conditions, we normalize to common baselines: A100 GPUs, 7B-70B parameter models, and standard prompt distributions. GPU utilization data is estimated from reported throughput and known hardware peak performance, following the methodology of DVFS-aware inference analysis (Park et al., 2025^[9]).

4. Application to AI Memory Series #

4.1 TTFT Improvement Analysis (RQ1) #

Our synthesis of published results across six disaggregated serving systems reveals consistent TTFT improvements ranging from 1.4x to 2.3x over colocated baselines.

The data reveals an important pattern: TTFT improvement and TPOT impact are inversely correlated. Systems achieving the highest TTFT speedups (ServerlessPD at 2.3x) maintain TPOT near baseline (1.05x) due to RDMA’s low-latency transfer, while hardware-specialized approaches (SPAD at 1.6x TTFT) show TPOT degradation (1.2x) due to slower inter-chip communication.

However, these improvements are not guaranteed. Recent analysis by Stojkovic et al. shows that disaggregation benefits depend heavily on request load — under light load, colocated serving can match or exceed disaggregated performance because the GPU is not contended (Zhao et al., 2026^[10]). The breakeven point typically occurs at 60-70% GPU utilization for colocated systems.

For the AI Memory series, this means disaggregation is primarily a high-utilization optimization. Systems running below capacity gain little from the architectural complexity of separated phases.

4.2 KV Cache Transfer Analysis (RQ2) #

KV cache transfer is the fundamental cost of disaggregation. The cache size scales linearly with context length, number of layers, and head dimensions. For a 70B parameter model with 80 layers of KV cache, transferring 32K tokens of context requires approximately 5GB of data.

Our analysis shows that interconnect choice creates order-of-magnitude differences in transfer time. At 32K context length, PCIe Gen4 requires approximately 32ms, RDMA 100Gbps requires 12ms, CXL requires 9.6ms, and NVLink requires 6ms. These transfer times must be weighed against prefill computation time — for a 70B model processing 32K tokens, prefill takes approximately 200-400ms, making a 32ms transfer overhead acceptable (8-16% overhead) but not negligible.

CXL-based disaggregation represents a promising middle ground. CXL-SpecKV demonstrated that CXL memory pooling enables near-NVLink transfer speeds with datacenter-scale deployability (Chen et al., 2026^[8]). Unlike NVLink, which requires physical proximity, CXL operates over standard PCIe physical layer and supports rack-scale pooling.

The chunked prefill approach, where KV cache is transferred incrementally during prefill rather than as a single batch after completion, can hide transfer latency. Sarathi-style chunked prefills pipeline computation and communication (Agrawal et al., 2025^[11]), reducing effective transfer overhead to near zero when chunk size is tuned to match network bandwidth.

4.3 GPU Allocation and Throughput Optimization (RQ3) #

The optimal ratio of prefill-to-decode GPUs depends on workload characteristics: prompt length distribution, generation length, and arrival rate.

Our analysis reveals distinct optimal ratios per workload type. Chatbot workloads (short prompts, long generations) peak at 50% prefill allocation, where both phases are balanced. Code generation workloads (medium prompts, long generations) optimize at 50-60% prefill allocation due to the higher compute demand of processing structured code prompts. Summarization workloads (long prompts, short generations) peak at 40% prefill allocation because the dominant decode phase needs more GPU capacity despite shorter generation lengths.

The compute intensity analysis explains these patterns. Prefill remains 82-95% compute-bound regardless of batch size, while decode transitions from 15% compute-bound at batch size 1 to 65% at batch size 64. This means decode-dedicated GPUs benefit strongly from large batch sizes — a key advantage of disaggregation, since decode instances can accumulate larger batches without prefill interference.

GPU utilization improves substantially under disaggregation. Colocated serving achieves only 45% prefill and 30% decode utilization due to mutual interference. Inter-GPU disaggregation raises this to 85% and 75% respectively, while hybrid approaches (combining inter- and intra-GPU disaggregation) achieve 82% and 80%.

Efficient request scheduling across the disaggregated pools further influences throughput. SwiftServe introduced hierarchical max-flow scheduling that dynamically adjusts prefill-decode allocation based on queue depths (Zhang et al., 2025^[12]). TD-Pipe proposed temporally-disaggregated pipeline parallelism that interleaves prefill and decode micro-batches across pipeline stages (Liu et al., 2025^[13]).

4.4 Energy Implications #

Disaggregation enables per-phase DVFS (Dynamic Voltage and Frequency Scaling), since prefill and decode have different optimal operating points. Park et al. demonstrated that prefill benefits from maximum GPU frequency while decode can operate at reduced frequency with minimal throughput impact (Park et al., 2025^[9]). SLO-aware DVFS policies that exploit this asymmetry achieve 15-25% energy savings while meeting latency targets (Zhao et al., 2026^[10]).

4.5 Multi-Round Inference #

PrefillShare addressed the multi-round conversation challenge in disaggregated serving, where repeated prefill operations waste computation on previously processed context. By introducing a shared prefill module that caches and reuses KV states across conversation turns, multi-round inference latency was reduced by 30-45% compared to naive disaggregation (Ivchenko, 2026^[2]). This connects directly to the semantic caching work covered in our previous article.

flowchart LR
    subgraph Prefill_Pool
        P1[GPU 1: Prefill]
        P2[GPU 2: Prefill]
    end
    subgraph Transfer_Layer
        KV[KV Cache Transfer]
        RDMA[RDMA / CXL / NVLink]
    end
    subgraph Decode_Pool
        D1[GPU 3: Decode]
        D2[GPU 4: Decode]
        D3[GPU 5: Decode]
    end
    P1 --> KV
    P2 --> KV
    KV --> RDMA
    RDMA --> D1
    RDMA --> D2
    RDMA --> D3
    D1 --> Output[Token Stream]
    D2 --> Output
    D3 --> Output

5. Conclusion #

RQ1 Finding: Disaggregation reliably improves TTFT by 1.4-2.3x across all evaluated systems, but only at GPU utilization above 60-70%. Measured by TTFT speedup over colocated baseline, the improvement is consistent across DistServe (2.0x), Splitwise (1.4x), Mooncake (1.7x), and ServerlessPD (2.3x). This matters for the AI Memory series because it confirms that memory architecture decisions — specifically where and how KV cache resides — directly determine inference latency.

RQ2 Finding: KV cache transfer overhead scales linearly with context length and ranges from 6ms (NVLink) to 32ms (PCIe Gen4) at 32K context. Measured by transfer time as a fraction of total latency, this overhead represents 3-16% of end-to-end inference time for 70B models. This matters for the AI Memory series because it identifies interconnect technology as the gating factor for disaggregated memory architectures — without fast transfer, the memory separation that enables better utilization becomes a bottleneck.

RQ3 Finding: Optimal prefill-to-decode GPU ratios are workload-dependent: 50% for chatbot, 50-60% for code generation, and 40% for summarization workloads. Measured by normalized throughput at optimal allocation, all workloads achieve >0.95 of theoretical maximum. This matters for the AI Memory series because it demonstrates that memory-aware scheduling must consider workload characteristics — there is no universal optimal configuration for KV cache distribution.

The next articles in this series will examine cache-aware request scheduling and batching strategies that build on disaggregated architectures, followed by an analysis of the memory hierarchy (DRAM, HBM, SSD) that underlies KV cache storage.

Data and code: github.com/stabilarity/hub