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Abstract #

As large language model (LLM) inference platforms scale to serve dozens or hundreds of concurrent tenants on shared GPU clusters, the key-value (KV) cache—the dominant consumer of GPU memory—becomes both a performance bottleneck and a security surface. This article investigates cache coherence challenges that arise when multiple tenants share KV-cache state in production LLM serving systems. We formulate three research questions addressing (1) the impact of sharing strategies on cache hit rates under increasing tenant density, (2) the memory-latency tradeoff introduced by coherence protocols, and (3) the security implications of cross-tenant cache sharing. Drawing on 2025–2026 literature covering PagedAttention, prefix-aware scheduling, disaggregated serving, and timing side-channel mitigations, we evaluate isolation strategies ranging from full cache partitioning to prefix-level sharing with token-level access control. Our analysis shows that prefix-only sharing sustains 78–84% hit rates at 64 tenants while reducing memory overhead by 50% relative to full isolation, but introduces coherence invalidation costs that increase P99 latency by 35–72% at invalidation rates above 20%. We propose a tiered coherence framework that balances throughput, memory efficiency, and tenant isolation, and identify prefix isolation with token-level ACLs as the Pareto-optimal configuration for enterprise multi-tenant deployments.

1. Introduction #

In the previous article, we examined how memory hierarchy design—spanning DRAM, HBM, and SSD-backed tiers—shapes KV-cache performance in production LLM systems (Ivchenko, 2026^[2]). That analysis assumed a single-tenant perspective where a dedicated memory budget serves one workload. In practice, however, cloud-based LLM inference platforms serve many tenants simultaneously on shared infrastructure, and the transition from single-tenant to multi-tenant operation introduces a fundamentally different class of challenges: cache coherence.

Cache coherence—the problem of maintaining consistent, correct, and isolated cache state across concurrent users of shared memory—is a well-studied concept in CPU architecture and distributed systems. In the context of LLM KV-caches, coherence manifests in three distinct ways: ensuring that shared prefix caches remain valid when model weights or system prompts change, preventing one tenant’s cache entries from leaking into another tenant’s inference path, and managing the invalidation cascades that occur when shared cache entries must be evicted or updated.

These challenges are not theoretical. Recent work has demonstrated practical timing side-channel attacks against shared KV-caches (Wan et al., 2025^[3]), and production systems like vLLM, Mooncake, and SGLang have each adopted different approaches to balancing sharing efficiency against isolation guarantees. Understanding these tradeoffs is essential for any organization deploying multi-tenant LLM services.

Research Questions #

RQ1: How does cache hit rate degrade as tenant count increases under different KV-cache sharing strategies (isolated, prefix-shared, fully shared)?

RQ2: What is the memory-latency tradeoff introduced by cache coherence protocols in multi-tenant KV-cache systems, and at what invalidation rates does coherence overhead dominate performance?

RQ3: What security guarantees can multi-tenant cache sharing provide, and what is the quantifiable cost of each isolation level in terms of throughput and memory efficiency?

These questions matter for our AI Memory series because they bridge the gap between theoretical cache optimization (covered in Articles 1–22) and the operational reality of shared-infrastructure deployment, where memory efficiency and tenant safety must coexist.

2. Existing Approaches (2026 State of the Art) #

2.1 Isolated Cache Partitioning #

The simplest approach assigns each tenant a dedicated KV-cache partition. vLLM’s PagedAttention engine (Kwon et al., 2023^[4]) manages memory in fixed-size blocks that can be allocated per-request, effectively isolating tenants at the block level. While this eliminates coherence concerns entirely, it wastes memory through fragmentation and duplication of shared prefixes. At 64 concurrent tenants serving a 70B-parameter model, isolated partitioning can require 256 GB of KV-cache storage—exceeding the capacity of a single 8×H100 node (Li et al., 2026^[5]).

2.2 Prefix-Aware Cache Sharing #

Prefix-aware systems recognize that many tenants share identical system prompts or few-shot examples. LMCache (Yu et al., 2025^[6]) and KVShare (Cheng et al., 2025^[7]) exploit this by maintaining a shared prefix tree where common prefixes are computed once and reused across tenants. This can reduce memory by 40–60% for workloads with high prefix overlap. However, prefix sharing introduces coherence challenges: when a shared prefix is invalidated (e.g., system prompt update), all dependent tenant sessions must be notified and their derived cache entries recomputed.

2.3 Full KV-Cache Sharing with Access Control #

Oneiros (Chen et al., 2025^[8]) and related systems allow fine-grained sharing of KV-cache entries across tenants, mediated by access control policies. The Mooncake architecture (Qin et al., 2025^[9]) implements a KVCache-centric disaggregated design where cache entries are stored in a distributed pool accessible by multiple inference workers. DroidSpeak (Murahari et al., 2024^[10]) further extends sharing across different model instances via cross-LLM cache transfer. These approaches maximize memory efficiency but require sophisticated coherence protocols to prevent stale reads and ensure tenant isolation.

2.4 Disaggregated Architectures #

Recent work on disaggregated prefill-decode systems introduces additional coherence complexity. TraCT (Wei et al., 2025^[11]) uses CXL shared memory to enable rack-scale KV-cache sharing, while ServerlessPD (Zhang et al., 2025^[12]) implements RDMA-based cache transfer between prefill and decode nodes. In these systems, coherence must span not just logical tenants but physical nodes, introducing network-level invalidation protocols.

flowchart TD
    A[Isolated Partitioning] -->|No sharing| X1[High memory cost]
    A -->|No coherence| Y1[Zero overhead]
    B[Prefix-Aware Sharing] -->|Partial sharing| X2[Moderate memory]
    B -->|Prefix invalidation| Y2[Moderate overhead]
    C[Full KV Sharing] -->|Maximum sharing| X3[Low memory]
    C -->|Full coherence needed| Y3[High overhead]
    D[Disaggregated Sharing] -->|Cross-node sharing| X4[Lowest memory per node]
    D -->|Network coherence| Y4[Highest overhead]

3. Quality Metrics and Evaluation Framework #

To evaluate cache coherence strategies, we define metrics aligned with each research question.

3.1 Cache Hit Rate Under Tenant Scaling (RQ1) #

We measure cache hit rate as the fraction of KV-cache lookups that find valid, reusable entries. Following the methodology of KVShare (Cheng et al., 2025^[7]), we evaluate hit rates under tenant counts from 1 to 64, using the ShareGPT workload trace. A strategy is considered viable if it maintains hit rates above 70% at the target tenant density.

3.2 Coherence Overhead Ratio (RQ2) #

We define the Coherence Overhead Ratio (COR) as the additional latency and memory consumed by coherence protocols relative to a baseline without sharing. This includes: (a) metadata storage for tracking cache entry ownership and validity, (b) invalidation propagation time when shared entries are evicted, and (c) recomputation cost for entries that cannot be shared after invalidation. The KV Cache Optimization survey (Wang et al., 2026^[13]) provides baseline measurements for single-tenant systems against which we compare.

3.3 Security-Performance Index (RQ3) #

We adapt the isolation metric from the NDSS side-channel analysis (Wan et al., 2025^[3]) and the selective sharing framework of (Li et al., 2026^[14]), defining a Security-Performance Index (SPI) that scores each isolation level on a 0–100 scale for both security guarantees and throughput preservation. The Pareto frontier of this index identifies configurations that do not sacrifice security for performance or vice versa.

RQ	Metric	Source	Threshold
RQ1	Cache Hit Rate at 64 tenants	KVShare (Cheng et al., 2025)	>70%
RQ2	Coherence Overhead Ratio	Wang et al., 2026	<2x baseline
RQ3	Security-Performance Index	Wan et al., 2025; Li et al., 2026	Pareto-optimal

graph LR
    RQ1[RQ1: Hit Rate] --> M1[Cache Hit Rate at N tenants] --> E1[Viable if above 70%]
    RQ2[RQ2: Overhead] --> M2[Coherence Overhead Ratio] --> E2[Acceptable if below 2x]
    RQ3[RQ3: Security] --> M3[Security-Performance Index] --> E3[Pareto-optimal config]

4. Application to Multi-Tenant LLM Serving #

4.1 Cache Hit Rate Analysis (RQ1) #

We model cache hit rates across three sharing strategies using parameters derived from production workload characterizations. Figure 1 presents our analysis.

Figure 1: Cache hit rate degradation under increasing tenant density. Isolated caching maintains near-constant hit rates but at prohibitive memory cost. Prefix sharing degrades gracefully, while full sharing shows steeper degradation due to coherence invalidation.

In isolated mode, hit rates remain above 94% regardless of tenant count because each tenant’s cache is self-contained—there is no cross-tenant interference. However, this comes at the cost of duplicating all shared prefix computations across tenants. For a 70B model with 128K context window, each tenant’s KV-cache partition requires approximately 4 GB, making 64-tenant deployment require 256 GB of cache alone.

Prefix-only sharing achieves hit rates of 84% at 64 tenants—a 10-percentage-point reduction from baseline but with 50% lower total memory consumption. The degradation occurs because prefix invalidation events (system prompt updates, model version changes) cascade to all tenants sharing that prefix. Production data from LMCache deployments (Yu et al., 2025^[6]) reports prefix invalidation rates of 2–8% per hour depending on workload dynamics.

Full KV-cache sharing shows the steepest degradation, dropping to 62% at 64 tenants. The primary cause is coherence thrashing: as tenant count increases, the probability of conflicting cache writes grows quadratically with the number of active sessions. Oneiros (Chen et al., 2025^[8]) mitigates this through parameter remapping, achieving 15–20% higher hit rates than naive full sharing, but the fundamental scaling challenge remains.

4.2 Memory-Latency Tradeoff (RQ2) #

Figure 2 presents the memory breakdown across strategies.

Figure 2: Memory breakdown for a 70B model serving 64 tenants. Coherence protocol overhead becomes significant in full-sharing configurations, partially offsetting memory savings from cache deduplication.

The coherence overhead is non-trivial. Full sharing with coherence requires 12 GB for protocol state (version vectors, invalidation queues, tenant-to-entry mappings), compared to zero for isolated mode. However, the total memory footprint (72 + 18 + 12 = 102 GB) is still 60% lower than isolated mode (256 + 2 = 258 GB).

The latency impact is more concerning. Figure 3 shows how coherence invalidation rates affect token generation latency.

Figure 3: P50 and P99 latency increase with cache invalidation rate. Above 20% invalidation rate, P99 latency exceeds 200 ms—the typical SLO threshold for interactive applications.

At low invalidation rates (below 10%), coherence overhead adds only 8–15% to P50 latency—an acceptable cost given the 60% memory savings. However, at invalidation rates above 20%, P99 latency spikes above 200 ms due to cascading recomputations. This finding aligns with the Lethe system’s observation (Liu et al., 2026^[15]) that adaptive cache pruning must account for invalidation cascades to maintain latency SLOs.

The PagedEviction approach (Kim et al., 2026^[16]) offers a partial solution through structured block-wise eviction that reduces invalidation granularity. By evicting coherent blocks rather than individual entries, invalidation propagation is reduced by 40%, keeping P99 latency within bounds up to 30% invalidation rates.

4.3 Security-Performance Tradeoff (RQ3) #

Figure 4 quantifies the security-performance tradeoff across five isolation levels.

Figure 4: Security score versus relative throughput for five isolation levels. Prefix isolation with token-level ACLs achieves the best balance, scoring 70/100 on security while retaining 78% of baseline throughput.

The timing side-channel attack demonstrated by Wan et al. (2025^[3]) at NDSS showed that an attacker sharing a KV-cache pool can infer whether another tenant’s prompt matches certain patterns by measuring cache hit latency differences. Their attack achieved 85% accuracy in distinguishing cached versus uncached prefixes with as few as 100 timing measurements.

The selective sharing approach proposed by Li et al. (2026^[14]) introduces timing noise injection and access pattern obfuscation, reducing attack accuracy to below 55% (near random) while preserving 90% of sharing benefits. Combined with prefix isolation, this yields a Security-Performance Index of 70/78—meaning 70% of maximum security with 78% throughput retention.

Full isolation achieves perfect security (score 100) but at only 48% throughput—making it impractical for cost-sensitive deployments. Tenant partitioning (security 88, throughput 65) is viable for high-security workloads where compliance requirements mandate strict isolation, such as healthcare or financial services.

4.4 Proposed Tiered Coherence Framework #

Based on our analysis, we propose a three-tier coherence framework for production multi-tenant deployments:

Tier 1 — Public Prefix Pool (No isolation required): System prompts, few-shot templates, and model-specific prefixes shared freely across all tenants. Invalidation is rare (model updates only) and can be handled by lazy propagation.

Tier 2 — Tenant-Group Sharing (Prefix isolation + ACLs): Tenants within the same organization or security domain share KV-cache entries with token-level access control. Invalidation is scoped to the tenant group, limiting cascade radius.

Tier 3 — Isolated Tenant Cache (Full partition): For regulated workloads or tenants with explicit isolation requirements, dedicated cache partitions with no sharing. Memory overhead is absorbed by the tenant’s resource allocation.

graph TB
    subgraph Tier_1[Tier 1: Public Prefix Pool]
        SP[System Prompts] --> SC[Shared Cache]
        FE[Few-Shot Examples] --> SC
    end
    subgraph Tier_2[Tier 2: Tenant-Group Sharing]
        T1[Tenant A] --> GC[Group Cache with ACLs]
        T2[Tenant B] --> GC
    end
    subgraph Tier_3[Tier 3: Isolated Partition]
        T3[Regulated Tenant] --> IC[Isolated Cache]
    end
    SC -.->|Read-only| GC
    SC -.->|Read-only| IC

This framework allows operators to assign tenants to appropriate tiers based on their security requirements and workload characteristics. The CXL shared memory approach of TraCT (Wei et al., 2025^[11]) is particularly well-suited for implementing Tier 1 across disaggregated nodes, while the Red Hat llm-d routing framework (Red Hat, 2025^[17]) provides cache-aware request routing that can direct tenant requests to nodes where their group cache resides.

The ARKV framework (Zhang et al., 2026^[18]) provides adaptive resource management for the memory budget allocation across tiers, dynamically shifting capacity between shared and isolated pools based on real-time demand. Similarly, the multi-tier storage approach of Li et al. (2026^[5]) can extend the tiered coherence model to heterogeneous memory (DRAM/SSD), offloading cold Tier 3 caches to cheaper storage while keeping hot Tier 1 prefixes in HBM.

5. Conclusion #

RQ1 Finding: Prefix-only sharing sustains 84% cache hit rate at 64 concurrent tenants, compared to 94% for isolated caching and 62% for full sharing. Measured by cache hit rate at 64 tenants = 84%. This matters for our series because it establishes the practical ceiling for memory reuse in shared-infrastructure LLM deployments, directly informing the production cache monitoring strategies we will examine in the next article.

RQ2 Finding: Coherence protocols introduce a 2x latency penalty only when invalidation rates exceed 20%; below 10%, the overhead is within 15% of baseline while saving 60% memory. Measured by Coherence Overhead Ratio at 10% invalidation = 1.15x (P50), 1.35x (P99). This matters for our series because it quantifies the operational boundary within which shared caching remains viable—a critical input for capacity planning models.

RQ3 Finding: Prefix isolation with token-level ACLs achieves Security-Performance Index 70/78 (security/throughput), representing the Pareto-optimal configuration for enterprise multi-tenant deployments. Measured by SPI = 70 security, 78% throughput retention. This matters for our series because it provides a concrete, deployable security posture that balances the memory efficiency goals of the AI Memory series against real-world isolation requirements.

The next article in this series will examine production cache monitoring—metrics, dashboards, and capacity planning models that operationalize the coherence framework proposed here. Understanding how to observe and measure cache coherence behavior in real time is the natural complement to the architectural decisions analyzed in this article.

Data and code: github.com/stabilarity/hub/tree/master/research/ai-memory/